A type of IC memory used in image processing is a static random access memory (SRAM) which can be used to orthogonally transpose an array of bits used to form an image. An efficient form of this memory is described in U.S. Pat. No. 4,736,442 invented by Cary D. Kornfeld, which is incorporated by reference herein. A description of part of that memory is summarized below and is reproduced in FIG. 1 herein.
Turning to FIG. 1, the memory is formed of a matrix of cells (0,0) . . . (8,8), wherein the first numeral designates rows of the matrix and the second numeral designates the columns of the matrix. The number of cells in the matrix is (9.times.9).
In order to write to the memory, data is applied via write drivers 3 to data lines 5 which are equal in number to the number of columns of cells. Each data line passes through columns of cells and is coupled to a port of each cell of that column.
Row select signals are applied via decoded row address lines 7 to the rows of cells. For a row write operation, a row select signal is applied to the corresponding addressed row of cells, and the data carried by the data lines 5 is written into and latched by the corresponding cells. For a row read operation, a row select signal is applied to the corresponding addressed row, and data from the cells is read out onto the data bus 5 and then sensed by the data bus sense amplifiers 6.
To read the data out of the memory in a direction orthogonal to the direction of writing, another set of data lines 9 running horizontally adjacent to rows of the matrix of cells, is used. Each of the lines 9 is coupled to a second port of each of a corresponding row of cells. Columns of cells, i.e. one cell of each row, are enabled to be read out to the lines 9 by means of column select signals applied to column select lines 11, which are derived from decoded column address signals.
It is also desired in this type of prior art memory to be able to load addressed columns of cells, in addition to addressed rows of cells as in the structure already described. This could be accomplished by separately driving and sensing data lines 9, which would be loaded with the data and once the desired column is enabled using the column enable lines 11, a column of data would be written into and latched in a column of cells. However, in order to avoid adding the associated multiple drivers and sense amplifiers (not shown), it is a feature of the invention described in the aforenoted patent that the column data is applied to the same data lines 5 as is used to load row data. By connecting the data lines 5 which pass through columns of cells, to the data lines 9 along a diagonal (as shown in FIGS. 4a and 4b of the aforenoted patent), data lines 5 can be used to load data for storage in rows of cells or for storage in columns of cells. The diagonal interconnection points of data lines 5 and 9 are shown as elements a, b, c, . . . i in FIG. 1 herein.
In operation, in general, a row select line 7 enables the first port and a column selection line 11 enables the second port. To load data into a column of cells, data is applied to data lines 5. This data is transferred via the diagonal connections a, b, c, . . . i to respective horizontally illustrated data lines 9. The data thus appears at the second port of the corresponding cells. A column of cells is then enabled by means of a column select line 11, and the corresponding column of cells latches the data which appears at the selected second ports of the column of cells.
Reading data from a column proceeds in a similar manner as writing, except that the data is read out of the rows or columns of cells via the diagonal connections to read amplifiers 6.
The above structure operates adequately for storing one bit per cell. However, in the case of multiple bits per cell, a significant practical problem is encountered. To understand this problem, a relatively simple example of a 2 by 2 cell array is illustrated in FIG. 2, in which each cell is comprised of 4 subcells, i.e. to store 4 bits per cell. A more complex design for implementing pixel data, for example, would have an array of 8.times.8 cells, with each cell storing 16 bits and thus requiring 16 subcells.
Each subcell in FIG. 2 is identified by a three digit number a/b/c contained within the subcell block shown, wherein a represents the row number, b represents the column number, and c represents the bit number. Hence cell 1/2/3 represents the fourth subcell in the third column of the second row; all rows, columns and bits start at 0. The more common term "bit" will be used interchangeably with subcell in the description below.
No address select signals or other control signals are shown in FIG. 2. For simplicity, only the orthogonal data paths are shown.
In order to write or read rows, 8 row data lines are required, which are shown as R(0)-R(7). The row data lines run through subcells of similar bit numbers and similar column numbers. For example, data line R(0) runs through subcells 0/0/0 and 1/0/0 (subcells having bit number 0 and column number 0), data line R(3) runs through subcells 0/0/3 and 1/0/3 (subcells having bit number 3 and column number 0), data line R(5) runs through subcells 0/1/1 and 1/1/1 (subcells having bit number 1 and column number 1), etc. The row data lines are arranged in two sets of 4 bits each (e.g. R(0)-R(3) and R(4)-R(7)). It should be noted that each row data line is actually formed of two separate conductors, since complementary pairs are typically used, i.e. RDL(0) and /RDL(0) for example.
The row data lines R(7:0) can run as illustrated vertically, since the data can be placed on a particular row data line and then a particular row can be enabled to have the data written into the subcells corresponding to the row data line, of that particular row. This works because adjacent subcells in the vertical direction all belong to different rows (the subcell row number designation a). Therefore all subcells in the vertical direction can share the same row data line pair.
However, to be able to write to columns, adjacent subcells in the horizontal direction of a particular cell have the same column number b, prohibiting the use of common horizontal data buses. In this subcell implementation, a column is four subcells wide, as indicated by the `b` value in each subcell's notation. Therefore, column data lines must run as illustrated horizontally the whole width of the array, in this example consisting of only two columns, in order to deliver data to the corresponding subcells in the different columns.
Thus for example, the column data line C(0) is coupled to subcells in the first row which have the same row number (0) and the same bit number (1), i.e. to subcells 0/0/0 and 0/1/0. Column data line C(3) is horizontally coupled to subcells 0/0/3 and 0/1/3, column data line C(6) is horizonally coupled to subcells 1/0/2 and 1/1/2, etc. In this case as well, each of the column data lines is typically comprised of a complemetary pair of leads.
Thus for the above example of an array of 2 rows.times.2 columns.times.4 bits per column, 8 column data lines must be used, (4 for the first row and 4 for the second row), i.e. 16 lines in total which are required to extend the width of the array. The above example has used a simplified array made up of only 2.times.2.times.4 for explanatory purposes.
In the more complex 8.times.8.times.16 bit application mentioned above, the memory would require 128 columns, each consisting of 16 bits, i.e. 256 horizontal column data lines would be required to pass along the entire width of the array. This huge number of lines would make the vertical dimension of the array greatly dependent on the data line width, rather than more dependent on the sum of the heights of the storage cells, leading to an inefficient use of space on the integrated circuit layout.
In the aforementioned prior art patent, a cell consisted of only one bit and there were no subcells. As a result, horizontally adjacent cells shared a common row but not a common column as in the case in the multibit cell also described above. Since in the former case the cells only have one bit per cell, the horizontal column data lines of the multibit cells are not required, and hence the additional area taken up by horizontal data lines would not be an issue.
However, in the more complex application described above, because of the multibit cell requirement, the bus saving structure described in the aforenoted patent cannot be used. A need therefore arises for addressing column data line access for multibit cell applications.